Single chip receivers can be made low cost and small size when the receiver's selectivity filter and demodulator are completely integrated on the same integrated circuit die or chip. To obtain reasonable power consumption, required for long battery live, the intermediate frequency (IF) is chosen to be relatively low, e.g. 200 kHz, or, preferably, Zero-IF.
The Direct-Conversion or so called Zero-IF receiver architecture has gained attention due to the absence of unwanted image reception, which can be problematic in Low-IF architectures. In turn, there are other problems in the Zero-IF architecture that must be solved, such as self mixing in the front-end circuitry, which causes unwanted direct current (DC) signal levels at the output of the mixers. Typically, complex servo loops, often implemented using high resolution Digital to Analog Converters (DACs), are used to remove the DC signal component. See U.S. Pat. No. 6,735,422 for an example of a servo loop solution. Once the servo loops have settled, the DC compensation is frozen such that low frequency signal components are not filtered out during the reception of the information.
FIG. 1 is a circuit diagram illustrating an example of a conventional Zero-IF receiver circuit 10. Note that, in the circuit of FIG. 1, the DC offset correction needs an Offset Voltage Level Detect Analog to Digital Converter 34, a digital Offset Voltage Detector 36, Control and Timing Logic 40, a DC Estimate combiner 56, a Gain compensation Amplifier 70, a Digital Filter 72, 74, and a DC Digital to Analog Converter (DAC) 76. When a complex demodulator is implemented, then this DC offset correction circuitry is required for both the I and Q channels. This typically adds significantly to the chip area required to implement the circuit and increases the cost of the receiver chip.
Conventional Zero-IF receiver architectures, such as the receiver illustrated in FIG. 1, use one or more DC filters to cancel the previously mentioned DC signal levels present in the IF chain. The DC cancellation will result in a notch at the center of the receive channel response as indicated in the frequency response curve shown in FIG. 2.
Some modulation types can withstand low frequency filtering in the middle of the channel. Direct-Conversion Receivers are well suited for those modulation types because the DC signal levels at the output of the mixer can be effectively canceled by a simple high pass filter. An example of a Direct-Conversion Receiver 100, such as may be found in the SA2400 part from Philips/NXP, is shown in FIG. 3. In this example, a Zero-IF receiver 100 has two DC filters 116, 118, 124, 126 per branch, which are illustrated in the circuit diagram as a block with a capacitor inside. The modulation type is Direct Sequence Spread Spectrum (DSSS) in accordance with IEEE standard 802.11b. This modulation technique can withstand some filtering around the center of the channel and the receiver architecture of FIG. 3 is well suited to this application.
However, other modulation types, such as On/Off Keying (OOK), Frequency Shift Keying (FSK), Gaussian Frequency Shift Keying (GFSK), Minimum Shift Keying (MSK), Phased Shift Keying (PSK), and Quadrature Phased Shift Keying (QPSK), are typically less robust against DC filtering and generally require other receiver techniques, such as the Zero IF approach illustrated in U.S. Pat. No. 6,735,422.